1. Field of the Invention
The present invention relates to an inner potential generating circuit and particularly to an inner potential generating circuit for use in a dynamic random access memory or the like.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a conventional inner potential generating circuit. Referring to FIG. 1, a potential at a power supply terminal 1 (connected to an external power supply not shown) and a potential at ground 2 are kept V.sub.DD and 0 volt, respectively. A pulse generating circuit 3 as an AC power supply receives electric power from the power supply terminal 1 and the ground 2 so that it generates a pulse signal .phi.. This pulse generating circuit 3 comprises a ring oscillating circuit using for example a MOS field effect transistor (referred to hereinafter as MOS FET). An output terminal of the pulse generating circuit 3 is connected to an electrode of a coupling capacitor 5 at a node 4. The other electrode of the coupling capacitor 5 is connected with a drain and a gate of a discharging MOS FET 7 at a node 6. The source of the discharging MOS FET 7 is connected to the ground 2. The other electrode of the coupling capacitor 5 is also connected to the source of a charging MOS FET 8 at a node 6. The drain and the gate of the charging MOS FET 8 are connected to a substrate potential output terminal 9. The substrate potential output terminal 9 is connected to a semiconductor substrate of a semiconductor device not shown (for example a dynamic random access memory). A parasitic capacitor 10 exists between the substrate potential output terminal 9 and the ground 2. The coupling capacitor 5, the discharging MOS FET 7 and the charging MOS FET 8 constitute a potential generating circuit 11. The potential generating circuit 11 receives the pulse signal .phi. of the pulse generating circuit 3 at the node 4 to charge the substrate so that the potential at the substrate potential output terminal 9 may be V.sub.SUB.
In the following, operation of the above described conventional inner potential generating circuit will be described. For the purpose of simplification of the explanation, it is assumed that the pulse generating circuit 3 comprises for example a complementary MOS FET circuit (referred to hereinafter as a CMOS circuit) and that the output signal of this circuit is a rectangular wave excited sufficiently between the potentials V.sub.DD and 0 volt at the power supply terminal 1 and the ground 2, the time required for the rise and the fall thereof being negligible compared with a cycle of the output signal. The MOS FET's 7 and 8 are n channel MOS FET's and a threshold voltage V.sub.TH is assumed to be 0 volt.
FIG. 2 shows by (a), (b) and (c), potentials V4, V6 and V9 at the nodes 4 and 6 and the substrate potential output terminal 9, respectively, in a transitional state at the "n"th cycle of the pulse signal after turning on of the external power supply in the above indicated case. Assuming that conditions V4=0 volt and V6=V9=V(n-1)&lt;0 are given immediately before the time t(n)0, V4 becomes V.sub.DD at the time t(n)0 and since impedance of the capacitor 5 is sufficiently smaller than the impedance of the MOS FET's 7 and 8, V6 is increased by V.sub.DD so that the condition V6=V.sub.DD -V(n-1)&gt;0 is satisfied. Since the MOS FET 7 is turned on and the MOS FET 8 is turned off in the case of V6&gt;0, the potential V6 becomes 0 at the time t(n)1 when the time nearly equivalent to a time constant defined by the capacitor 5 and the MOS FET 7 passed and V6=0 is maintained till the time t(n)2 when the potential changes next. Since the MOS FET 8 is turned off during the period of V6=0, the potential V9 does not undergo any change and V9=V(n-1) is maintained. When the potential V4 becomes 0 volt at the time t(n)2, the potential V6 becomes V6=-V.sub.DD &lt;0 volt for the same reason as described above in the case of the time t(n)0. However, at the time t(n)2, the MOS FET 7 is turned off and the MOS FET 8 is turned on oppositely to the above described case. Accordingly, before the time t(n)3 attained by a lapse of time nearly equivalent to a time constant defined by the capacitors 5 and 10 and the MOS FET 8, the potentials V6=-V.sub.DD and V9=V(n-1) are changed to V6=V9=V(n)=V(n-1)-.DELTA.V(n)&lt;0 and the condition V6=V9=V(n) is maintained till the time t(n+1)0 when V4 changes next. Assuming that the capacitance values of the capacitors 5 and 10 are C5 and C10, a relation between V(n) and V(n-1) becomes as indicated in the following equation, if the law of invariability of electric charge is applied around the change from the time t(n)2 to the time t(n)3. EQU (C5+C10)V(n)=-C5V.sub.DD +C10V(n-1)
This equation can be changed as follows. EQU (C5+C10)(V(n)+V.sub.DD)=C10(V(n-1)+V.sub.DD)
If V(0)=0 is applied, the following equation is obtained. EQU V(n)=-V.sub.DD [1-{C10/(C10+C5)}.sup.n ] (1)
Since C10/(C10+C5)&lt;1, it can be seen that as n increases, V(n) approaches -V.sub.DD.
The equation (1) is established in the case of the threshold voltage V.sub.TH of the MOS FET's 7 and 8 being 0 volt. However, if transistors of the enhancement type of V.sub.TH &gt;0 volt are used as the MOS FET's 7 and 8, the potential V6 becomes equal to V.sub.TH at the above stated time t(n)1 when the MOS FET 7 in the on state turns off and, similarly, the potential V9 becomes V6+V.sub.TH at the time t(n)3 when the MOS FET 8 in the on state turns off. Thus, in the case of the enhancement type MOS FET's, the following equation for V9 similar to the equation (1) is obtained with regard to V9(n). EQU V9(n)=-(V.sub.DD -2V.sub.TH)[1-{C10/(C10+C5)}.sup.n ] (2)
Noticing that the time concerned is obtained by multiplication of the above indicated n by the value of the cycle of the pulse signal, it can be seen from the equation (2) that when the power supply V1 is turned on at the time t0 to attain V.sub.DD as shown by (a) of FIG. 3, the potential V9(V.sub.SUB) of the substrate potential output terminal 9 starts to decrease from 0 volt at the time t0 and attains -(V.sub.DD -2V.sub.TH) at the time t1 as shown by (b) of FIG. 3.
Thus, based on the above described principle, the conventional inner potential generating circuit generates internally and makes use of negative potential in the substrate equal to -(V.sub.DD -2V.sub.TH).
However, the above described conventional inner potential generating circuit involves the below described problems such as a considerable loss of electric power.
In a dynamic random access memory (referred to hereinafter as a dynamic RAM) to which the above described circuit is mainly applied, there is a large difference in the value of current of the substrate for returning the above stated V.sub.SUB (or V9) to the ground potential, dependent on whether the dynamic RAM is in an operation state such as reading, writing or refreshing state, or in a standby state. In case of a recently developed 256K-bit or 1M-bit dynamic RAM, the current of the substrate in the operation state is several tens of .mu.A and the current of the substrate in the standby state is several tens of pA. In a microcomputer or the like, a large storage capacity is often formed only by several hundreds of dynamic RAM's. If one word is composed of 8 bits in such a case, only about one chip out of 100 chips is related with reading and writing operation and the other chips are in a standby state. However, since the conventional inner potential generating circuit is adapted for operation with a large current in the substrate, there is involved a problem that consumption of electric power is increased in the standby state. This problem will be briefly explained in the following.
Although in the above description in connection with FIG. 1, existence of the parasitic capacitor 12 between the gate of the discharging MOS FET 7 and the ground 2 can be disregarded, the parasitic capacitor 12 becomes a problem in the standby state. If the existence of the parasitic capacitor 12 can be disregarded, the potentials V9(V.sub.SUB) and V6 attain -(V.sub.DD -2V.sub.TH) and -(V.sub.DD -V.sub.TH), respectively and accordingly the MOS FET's 7 and 8 are both turned off. Thus, the node 6 as an end of the coupling capacitor 5 is brought into a floating state, whereby charging or discharging current does not flow in the capacitor 5 and there is no consumption of electric power. However, if the parasitic capacitor 12 exists, charging or discharging current flows in the parasitic capacitor 12 through the capacitor 5 and consumption of electric power occurs. The parasitic capacitor 12 is formed through a depletion layer 13 between the channel 5y and the substrate 9a, for example as shown in FIG. 4, in case where the coupling capacitor 5 is formed by a MOS channel capacitor with the gate electrode 5x and the channel 5y being connected to the node 4 and the node 6, respectively. The coupling capacitor 5 shown in FIG. 4 comprises a gate insulating film 14 and an n.sup.+ diffusion region 15 for obtaining an electrode from the channel 5y. In FIG. 4, although the parasitic capacitor 12 is connected to the substrate 9a, namely, the substrate potential output terminal 9, the potential of the substrate 9a is almost constant and this structure is equivalent to a structure viewed from the standpoint of AC, in which the parasitic capacitor 12 is connected to the ground 2. If comparison is made between the capacitance values per unit area of the gate electrode 5x and the substrate 9a with respect to the channel 5y, the capacitance value per unit area of the substrate 9a is approximately 1/10 of that of the gate electrode 5x and accordingly the capacitance value of the parasitic capacitor 12 becomes approximately 1/10 of that of the coupling capacitor 5. Since the capacitance value of the coupling capacitor 5 is as large as 100 pF in the case of a 1M-bit dynamic RAM, 1/10 of the capacitance value of the capacitor 5 becomes a considerably large value.
More specifically, although charging and discharging values for the capacitor 5 in the operation state approach substantially to 0 according to the decrease of the potentials V6 and V9, charging and discharging values for the capacitor 5 in the standby state are not lowered because a pulse generator 3 directly charges and discharges effectively the capacitor 12 having a capacitance value approximate to 1/10 of that of the capacitor 5, without regard to the capacitor 5. As a result, even in the standby state, an amount of electric power almost equal to that in the operation state is consumed.
Another prior art technique of interest to the present invention is disclosed in "A 20ns Static Column 1Mb DRAM in CMOS Technology" by Katsuyuki Satoh et al., Feb. 15, 1985, pp. 254-255. According to a method disclosed in this document, a potential of a semiconductor substrate of a semiconductor device is made constant by always operating a potential generating circuit with low consumption of electric power to supply leakage current of the semiconductor substrate and by operating a potential generating circuit with a large charging capacity during a period of low level of a raw address strobe signal RAS (namely, during a period of the operation state of the semiconductor device) and/or during a period when the potential of the substrate exceeds a prescribed threshold voltage. If such a method is put into practical use, consumption of electric power in the standby state could be decreased. The above stated document discloses a back bias level detector as a circuit for detection of an excess of the potential of the substrate over the prescribed threshold voltage. However, the above stated document only discloses a circuit configuration of the back bias level detector (in FIG. 6) and gives no indication of a concrete content thereof. Consequently, the manner in which the back bias level detector detects an excess of the potential of the substrate over the prescribed threshold voltage is not clearly indicated in the above stated document. As is analogized from FIG. 6 of the above stated document, it seems that an inverter provided in the back bias level detector performs the above stated detection. However, the inverter does not have good sensitivity and if the input signal comes very close to the threshold voltage, it cannot be determined whether the output of comparison is of a high level or of a low level. Therefore, if the potential of the substrate is controlled by using such a back bias level detector, the potential of the substrate becomes unstable in the vicinity of the threshold voltage and cannot be made constant.